I’m more familiar with RISC-V than I am with ARM though it’s my understanding they’re quite similar.

• ARM/RISC-V are load-store architectures, meaning they divide instructions between loading/storing and doing computation. x86 on the other hand is a register-memory architecture, having instructions that do both computation as well as loading/storing.

• ARM/RISC-V also have weaker guarantees as to memory ordering allowing for less synchronization between cores, however RISC-V has an extension to enforce the same guarantees as x86 and Apple’s M-series CPU have a similar extension for ARM. If you want to emulate x86 applications on ARM/RISC-V these kinds of extensions are essential for performance.

• ARM/RISC-V instructions are variable width but only in a limited sense. They have “compressed instructions” - 2 bytes instead of 4 - to increase instruction density in order to compete with x86’s true variable width instructions. They’re fairly close in instruction density, though compressed instructions are annoying for compilers to handle due to instruction alignment. 4 byte instructions must be aligned to 4 bytes, so if you have 3 instructions A, B and C but only B has a compressed version then you can’t actually use it because there must be 4 bytes between instructions A and C.

• ARM/RISC-V also makes backwards compatibility entirely optional, Apple’s M-series don’t implement 32-bit mode for instance, whereas x86-64 still has “real mode” for running 16 bit operating systems.

There’s also a number of other differences, like the number of registers, page table formats, operating modes, etc, but those are the more fundamental ones I can think of.

Up until your post I had thought it exactly was the size of the instruction set with x86 having lots of very specific multi-step-in-a-single instruction as well as crufty instruction for backwards compatibility (like MPSADBW).

The MPSADBW thing likely comes from the hackaday article on why “x86 needs to die”. The kinda funny thing about that is MPSADBW is actually a really important instruction for (apparently) video decoding; ARM even has a similar instruction called SABD.

x86 does have a large number of instructions (even more so if you want to count the variants of each), but ARM does not have a small number of instructions and a lot of that instruction complexity stops at the decoder. There’s a whole lot more to a CPU than the decoder.

compressed instruction set /= variable-width […]

Oh for sure, but before the days of super-scalars I don’t think the people pushing RISC would have agreed with you. Non-fixed instruction width is prototypically CISC.

For simpler cores it very much does matter, and “simpler core” here can also could mean barely superscalar, but with insane vector width, like one of 1024 GPU cores consisting mostly of APUs, no fancy branch prediction silicon, supporting enough hardware threads to hide latency and keep those APUs saturated. (Yes the RISC-V vector extension has opcodes for gather/scatter in case you’re wondering).

If you can simplify the instruction decoding that’s always a benefit - moreso the more cores you have.

Then, last but not least: RISC-V absolutely deserves the name it has because the whole thing started out at Berkeley.

You’ll get no disagreement from me on that. Maybe you misunderstood what I meant by “CISC-V would be just as exciting”? I meant that if there was a popular, well designed, open source CISC architecture that was looking to be the eventual future of computing instead of RISC-V then that would be just as exciting as RISC-V is now.

The original debate from the 80s that defined what RISC and CISC mean has already been settled and neither of those categories really apply anymore. Today all high performance CPUs are superscalar, use microcode, reorder instructions, have variable width instructions, vector instructions, etc. These are exactly the bits of complexity RISC was supposed to avoid in order to achieve higher clock speeds and therefore better performance. The microcode used in modern CPUs is very RISC like, and the instruction sets of ARM64/RISC-V and their extensions would have likely been called CISC in the 80s. All that to say the whole RISC vs CISC thing doesn’t really apply anymore and neither does it explain any differences between x86 and ARM. There are differences and they do matter, but by an large it’s not due to RISC vs CISC.

As for an example: if we compare the M1 and the 7840u (similar CPUs on a similar process node, one arm64 the other AMD64), the 7840u beats the M1 in performance per watt and outright performance. See https://www.cpu-monkey.com/en/compare_cpu-amd_ryzen_7_7840u-vs-apple_m1. Though the M1 has substantially better battery life than any 7840u laptop, which very clearly has nothing to do with performance per watt but rather design elements adjacent to the CPU.

In conclusion the major benefit of ARM and RISC-V really has very little to do with the ISA itself, but their more open nature allows manufacturers to build products that AMD and Intel can’t or don’t. CISC-V would be just as exciting.

Kinda. IANAL, but here’s my understanding: If you’re explicitly dual-licensing and publish the proprietary license then contributions can be assumed to also follow the same dual licensing. You’d need to be extremely careful with writing the proprietary license though, since your business is now using non-employee proprietary code.

If you write “the copyright holder may choose to allow an entity to use this work”, then you do actually need permission from every contributor. If you write “this work may be copied, modified and redistributed freely by Blah enterprises” now the business cannot be sold without losing access (or possibly have it’s name changed). If you write “Neshura may freely copy, modify and redistribute this” then you can’t be fired or move jobs without the company losing access.

You can also never ever change this license, since every contributor needs to agree. So if a mistake is made when writing it you’re just fucked.

On the other hand with a CLA that transfers copyright ownership you don’t need to dual-license at all since everything already belongs to the business. Much less risky.

Only until you have any other contributor, as you’re then no longer the sole copyright holder. If you still want to work like that you’ll need a CLA.

TLDs are valid in emails, as are IP V6 addresses, so checking for a . is technically not correct. For example a@b and a@[IPv6:2001:db8::1] are both valid email addresses.

Mesa isn’t a kernel driver. AMDGPU is the name of the kernel module and it’s primarily developed by AMD. Mesa provides OpenGL, Vulkan, etc. implementations and is funded by AMD, Intel and Valve (among others). There’s also AMDGPU-PRO which is a proprietary alternative to Mesa from AMD.

AMDGPU is open source: https://github.com/radeonopencompute/rock-kernel-driver/, it’s also upstreamed into Linux. The firmware is a binary blob though.

They’re handing out magic beans with the selling point being that they can’t take them away from you once you get them.

And that’s not even true in any practical sense. If reddit decides that the token in your crypto wallet is invalid, then it’ll stop working on reddit. And since they’re the only issuer every possible use is going to be tied to reddit in some sense.

AptX and AptX LL are not the same thing. AptX has the same latency as LDAC and SBC: >200ms; whereas AptX LL is actually decent at ~30ms. AptX is supported by Windows out of the box, AptX LL is not.

From what I’ve seen this isn’t true. Search for “Windows AptX LL” and you’ll see dozens of ways you might install drivers that add support. The most common advice seems to be to buy a dongle that supports it.

AptX LL indeed has ~30ms of latency at the cost of bitrate, but last I checked it’s not supported by Windows out of the box. It’s also been generally dropped in favor of the higher latency AptX Adaptive due to requiring a dedicated wireless antenna. The default experience of Bluetooth is still >200ms of latency. Also 30ms is 4.2 frames at 140Hz.