I’ll explain myself. I’m doing a small project using a few dependencies, so I have to add them when I call gcc. Everything else is really easy. I just have c files and header files. I find it really cumbersome to have to tell make what headers go with what c files when they have the same name. I don’t see why we don’t have a build system where you simply have to give a project folder with the name of source file with the main() function, give the name of the output executable, the external dependecies to be called with gcc, and that’s it. Everything else can be automatically detected and linked apropriately, even with multiple folders inside the project folder. Does something like that exist that’s simple to use, or is this doable in make?

  • smpl@discuss.tchncs.deEnglish
    1·
    1 year ago

    There’s a lot of tricks you can use in Makefiles. I recommend reading the infopages info make. If your .c and .h files really have the same name, you should be able to get away with this rule %.c: %.h, but it is worth it to read the infopages.

    Also worth mentioning is gcc -MM filename.c which will generate a Makefile rule with the (non-system) headers included in filename.c.

    Good luck with you project!

  • lysdexic@programming.devEnglish
    21·
    1 year ago

    I don’t see why we don’t have a build system where you simply have to give a project folder with the name of source file with the main() function, give the name of the output executable, the external dependecies to be called with gcc, and that’s it.

    But we do. Check out CMake.

    https://cmake.org/examples/

    Originally CMake was a higher level abstraction over make, and generated makefiles based from the high-level project description. Nowadays it supports other build automation tools, such as Ninja, Visual Studio, Xcode, etc.

  • 0x0@programming.devEnglish
    1·
    1 year ago

    make has special variables you can use, some people will suggest cmake, others will mention pkgconfig.

  • suprjami@lemmy.sdf.orgEnglish
    1·
    1 year ago

    What you wish for is how I use make. Off the top of my head, something like this:

    EXEC = programname
SOURCES = $(wildcard *.c)
OBJECTS = $(SOURCES:.c=.o)

all: $(EXEC)

$(EXEC): $(OBJECTS)

%.o: %.c %.h

.PHONY: all clean

clean:
        rm -f $(EXEC) $(OBJECTS)

    Then just run make and it compiles and links all .c files into the executable. Each .c file needs a .h with the same name. Remove the %.h if you don’t like that requirement.

    From memory you might need a .c and .h file with the same name as the executable.